Enhancement mode MOSFET

Physical structure of Enhancement type MOSFET

N-channel Enhancement type MOSFET consists of a p type semiconductor substrate on which two n+ regions are grown as shown in the figure.

P-channel Enhancement type MOSFET consists of a N-type semiconductor substrate on which two P+ regions are grown. MOSFET is a four terminal device with the terminals being source gate, drain along with body terminal which is often shorted to source, so effectively only three terminals are used for control. A layer of silicon dioxide is grown on the substrate covering drain and source regions. Metal contacts are provided for all the three terminals.

 

Electrons flow from source to drain hence the conventional current of positive charge carriers flows from drain to source. It is a symmetric device either of the N+ regions can be used as source or drain. The circuit symbol of FET is as shown in the figure (a) with the arrow on source terminal shows the direction of normal current flow from drain to source.

Enhancement Mode MOSFET

Enhancement Mode MOSFET

As mentioned before often body terminal is shorted to source, hence the circuit can be modified and can be redrawn as fig (b). The space between two lines in the circuit symbol of FET indicates the fact that the gate is insulated from the body of the device through silicon dioxide insulating layer.

Operation of Enhancement type MOSFET

In Enhancement mode MOSFET the combination of Al metal contact, SiO2 layer, Semiconductor substrate act like a capacitor with silicon dioxide layer as dielectric. When a positive voltage is applied to the gate the bound charge displacement in SiO2 is as shown below. The electric field induced by external gate voltage repels the holes in p-type substrate adjacent to the silicon dioxide layer and the substrate will be depleted. Simultaneously it attracts the electrons in the N+ regions. As we continue to increase the gate to source voltage soon a n-type channel will be induced. The value of Vgs at which this happens is known as

Induced charge in SiO2 layer

Induced charge in SiO2 layer

Threshold voltage denoted by Vt. After the channel is induced if we apply small drain to source voltage electron current flows from source to drain through the induced N-channel. As we increase Vds continuously Ids (Conventional current flows from drain to source) also increase continuously. When Vds reaches Vdsat=Vgs-Vt the drain current reaches maximum and is in saturation. The channel at the drain end will be pinched off and further increase in the Vds will not have any effect on the drain current theoretically. But practically as Vds is increased further the pinch off end of the channel will move away from the drain towards the source. The voltage across the channel remains at Vdsat the extra voltage appears across the narrow depletion region between the drain and the pinch off end. This effect is termed as channel length modulation as effective channel length gets modulated by varying Vds. As you increase Vds further entire channel will be pinched off and breaks down (high currents flow in the device, generally this will not cause permanent damage to device).

Enhancement MOSFET Operation-1

Enhancement MOSFET Operation-1

Enhancement MOSFET Operation-2

Enhancement MOSFET Operation-2

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