Clocked RS Flip flop

In digital circuits the output of any circuit should not only depends on inputs of the circuit, in-addition to the inputs some sort of triggering mechanism should be provided for synchronized operation digital circuit which enables to provide a real time data at the output of the circuit. Consider a digital circuit with two gates connected in series with each gate delay of 1ms. In this condition the output of the first gate will be available after 1 ms of input data triggering time. The second gate provides the output within the same time with out waiting for the first gate output and this may results in wrong output of digital circuit. If an external clock cycle is provided to trigger the two gates at the same time will provide a real time output at the end of the digital circuit. In RS flip flop as soon the inputs R & S available the change in output state will results, so to control this state change according to the input a triggering clock is provided in addition to the input. This circuit is clocked RS flip flop.


Clocked RS Flip flop With NOR gates

clocked SR FF with NOR Gate

clocked SR FF with NOR Gate

The above circuit shows the clocked RS flip flop with NOR gates and the operation of the circuit is same as the RS flip flop with NOR gates when the clock is high, but when the clock is low the output state will be “No Change State”. Let us see this operation with help of above circuit diagram:

1) When the clock is Low i.e ‘0’, the outputs of two input and gates will be ‘0’ for any input of S & R. The 0-0 input to the RS flip flop with NOR gates results in “NO CHANGE STATE” at the output. This ensures for the clock zero or low condition the output will remains in the same state.

2) When the clock is high the input AND gates acts as a input follower i.e. when the other input is 0 output will be zero or if the input is ‘1’ output will be ‘1’. In this case the RS flip flop acts according to the input S&R and changes its state according to the input.

Clocked RS Flip flop with NAND Gates


Clocked SR FF with NAND

Clocked SR FF with NAND

It is same as the above circuit in which the AND gates and NOR gates are replaced with NAND gates as shown in below figure.

Clocked SR Flip flop Truth table

SR Flip flop truth table
Clock S R Qt+1
0 Qt
1 0 0 Qt
1 0 1 0
1 1 0 1
1 1 1 Ambiguity state

Characteristic Table of SR Flip flop

Characteristic table shows the relation ship between input and output of a flip flop. The characteristic table of SR Flip flop is shown below. In this the Q(t) is the output at clock of t and Q(t+1) is the output at next clock pulse i.e. t+1.

Characteristic table for SR Flip Flop
S R Qt Qt+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 Φ
1 1 1 Φ

Characteristic Equation of an SR Flip flop


By the above truth table the characteristic equation or input output relation equitation of SR Flip flop can be obtained by using karnaugh Maps method as shown in below.

The characteristic equation by the above karnaugh map is shown below.


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