D Flip flop circuit operation

The RS flip flop has two data inputs: S and H. To store a bit in the SR flip flop the two input signals are needed i.e. for storing high bit S should be high bit and for storing low bit R should be high. This two signals to drive to drive the flip flop to store the data is a disadvantage in many applications. So to avoid this disadvantage a D Flip flop is introduced which needs only one single input.

D flip flop is also called as DATA flip flop as it is stores a bit of data. i.e. the input data applied at the input D, it changes the output state according to input and remains in the same state until the input changes.


Delay flip flop: D flip flop also called as delay flip flop where it can be used to introduce a delay in the digital circuit by changing the propagation delay of the flip flop. Here the input data bit at D will reflects at the output after a certain propagation delay.

D flip flop Circuit

The D flip flop is formed by sorting the S & R input signals with a NOT gate in between the two input signals. It forms a single input which is called D. This configuration is introduced to use SET and RESET conditions of SR flip flop by omitting the other two conditions. 

D Flip flop Circuit diagram

D Flip flop Circuit diagram

Figure shows the unclocked D flip flop where the input bit D drives the S input and the complement D drives the R input. Therefore a high in D sets the output high and output reset is set by the D low. The Flip flop will change its state as soon as the input D changes. This UN-clocked D flip flop use is very less.

Clocked D Flip Flop

Clocked D flip flop

Clocked D flip flop

Figure shows the Clocked Flip flop with additional two and gates with two inputs are clock and D. When the clock is low it disables the two AND gates and prevents the Flip flop from changing the states. When a clock is high, it is important as the flip flop output state depends on the input D bit. A high D sets the flip flop output high and a low D resets it. Based on the input clock triggering mechanism the d flip flops are divided as level triggered and edge triggered flip flops.

D flip flop Truth table

0 * Last State
1 0 0
1 1 1

D Flip Flop Characteristic Table

D Qt Qt+1
0 0 0
0 1 0
1 0 1
1 1 1

D Flip Flop Characteristic Equation

By observing the above characteristic table the characteristic equation of D flip flop can be written as

Level Triggered D flip flop

The output changes when the clock level is high and it remains in the same state when the clock level goes low. This is called D Latch and it is not normally used configuration.

Edge triggered D Flip flop

The output changes when the clock goes from low to high or high to low. if the flip flop triggers for the clock low to high transition then it is called positive edge triggering and if it triggers for the clock high to low transition then it is called negative edge triggering.

Edge triggered D flip flop

Edge triggered D flip flop

In the above shown edge trigger circuit, input differentiators circuit with capacitor and resistor provides a positive spikes output for the rectangular clock input. That is if the RC time constant is less compared to edge transition delay of the clock the capacitor charges quickly and reaches its peak value. This peak value triggers the two AND gates and the input data bit will fed to the flip flop which stores the data. At high level clock there will not any change in voltage to capacitor so it starts discharging and it again charges for the next low to high clock transition. 

D Flip Flop with PRESET and CLEAR

PRESET is the an input to the D flip flop which sets the output data to High i.e. 1. and CLEAR is also an input which clears the output data or output state. A high PRESET forces Q to 1; a high CLEAR resets Q to 0. Figure shows clocked flip flop with PRESET and CLEAR inputs.

Clocked D FF with PRESET and CLEAR

Clocked D FF with PRESET and CLEAR

In the above circuit irrespective of the AND gates out, if the PRESET input is high the OR gate out directly sets the S input which makes Q to 1and in the same way if CLEAR input is high it resets the Q to 1.

Applications of D flip flop

  • The Edge triggered D flip flops are used in the sampling circuits to sample the date at particular time interval. i.e. at a sharp interval when the clock changes from low to high the input data will be delivered to the output and it remains the same until the next clock low to high. We can adjust the sampling intervals by changing the clock pulse widths.
  • It is used as a buffer to store the intermediate data
  • It is also used to introduce the delay in the circuits.


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