Jk flip flop

JK Flip flop is the ideal and important memory element which behaves the same fashion  as RS flip flop except the condition where R & S equals to 1. It is a forbidden in RS flip flop, the JK flip flop is an improved version which avoids this prohibited or impracticable state and converts in to toggle state. i.e. when J=1 and K=1 the output is the inversion of the last state. J and K in the JK flip flop means Jack and Kilby who invented this flip flop combination. This toggling condition is mostly used in the counters.

 

JK Flip flop operation

JK flip flop circuit diagram

JK flip flop circuit diagram

Figure shows the circuit diagram of JK flip flop in which two AND gates are placed input to the SR flip flop. One input of AND gate is J or K and second input is the feedback parameter of output, in a summarized way the inputs of first AND gate is J &~Q (Q bar) and the second gate inputs are R & Q. A clock signal is provide to the both AND gates for enabling or disabling the flip flop operation. The following points shows the operating conditions of JK flip flop:

  1. When J & K are low(i.e. 0), the two AND gates will disable irrespective of the Q & ~Q and two inputs to S&R FF will be zero which gives a no state condition. This condition is called latched condition as the flip flop retains its last value.
  2. When J is Low and K is High the upper or first AND gate disables, therefore there is no way to set the output of flip flop only the flip flop will be reset if the lower AND is high (i.e. 1). i.e. when the second input of lower AND gate Q is high then the output becomes High which sends a reset signal to SR flip flop and resets the flip flop (Q changes from 1–>0). Once FF resets Q becomes 0 and lower AND also disables and leads to no change condition of flip flop even the clock pulse is high.
  3. When J is High & K is Low, the lower AND gate gets disables which disables the resetting condition of flip flop. so the flip flop can only be set  if the upper AND gate is enable. When a Q is low ~Q will be high, this drives the upper AND gate to high with J is already high. The high output of upper AND gate drives the S input of SR flip flop which sets the flip flop output to high (Q=1). After this again the two AND gates are disabled because of ~Q=0 in this condition and it leads to no change condition.
  4. When J & K is High both AND gates can be enabled which is possible to SET or RESETS the flip flop. It is very important condition as it toggles the flip flop output states. Suppose if Q is high (FF last state) then lower AND gate enables which sends a reset signal to the flip flop and the output becomes Low. If Q is low ~Q will be high thus enables the upper AND gate which delivers a set signal to the flip flop and the output becomes High. This is illustrated as the clock is enabled and inputs J&K high the flip flop will be toggling mode and complements its output from its last output.

The above operation is summarized and shown in the truth table below.

J K Qt+1 Action
0 0 Q Latched ( No change)
0 1 0 Reset
1 0 1 Set
1 1 Q(bar) Toggle

Characteristic table of JK flip flop

This table shows the input and output relationship for the given clock pulses.

J K QT QT+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Characteristic equation of JK flip flop

Why JQ and KQ(bar) connection is not envisaged in JK Flip flop

In JK flip flop the output Q is connected to lower AND gate with K input and ~Q is connected to upper AND gate with J input. The connection of JQ and K~Q is not recommended because for this combination the toggling will not happen. Suppose for JK=11 condition if Q is low and connected with J to upper AND gate results in 01 condition at the input of SR flip flop which resets the flip flop and the output will be the same with out any change.

JK Flip flop Symbol

 

JK FF Level triggered symbol

JK FF Level triggered symbol

JK FF positive edge triggered sybol

JK FF positive edge triggered sybol

JK FF negitive edge triggered sybol

JK FF negitive edge triggered sybol

 

 

Race around condition of JK Flip Flop

In JK flip flop as long as clock is high for the input conditions J&K equals to the output changes or complements its output from 1–>0 and 0–>1. This is called toggling output or uncontrolled changing or racing condition. Consider above J&K circuit diagram as long as clock is high and J&K=11 then two upper and lower AND gates are only triggered by the complementary outputs Q and Q(bar). I.e. in any condition according to the propagation delay one gate will be enabled and another gate is disabled. If upper gate is disabled then it sets the output and in the next lower gate will be enabled which resets the flip flop output.

Steps to avoid racing condition in JK Flip flop:

  1. If the Clock On or High time is less than the propagation delay of the flip flop then racing can be avoided. This is done by using edge triggering rather than level triggering.
  2. If the flip flop is made to toggle over one clock period then racing can be avoided. This introduced the concept of Master Slave JK flip flop.

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