SR Flip Flop Circuit Operation

SR Flip Flop is a basic type of a flip flop which has two bistable states active HIGH (1) or LOW(0). The flip flop circuit remains in the same output state indefinitely until some input is applied to change the state which in this case S and R. As the name specifies these inputs are SET and RESET, it is called as SET-RESET flip flop. The input S will be 1 to set the output state High and R will be 1 to reset the output state Low. I.e. in SR flip flop the output state changes when the input signals S & R are complement to each other.

 

S-R Flip Flop Operation With NOR Gates

SR Flip Flop With NOR Gates

SR Flip Flop With NOR Gates

The SR flip flop with NOR gates in which each  NOR gate output is fed back as an inputs to one of the input of the other NOR Gate is shown in figure. The other inputs are connected to S and R input lines and the NOR gates outputs are denoted as Q and ~Q which are complement to each other. i.e if Q is ‘0’ ~Q will be ‘1’ and vice verse.

SR Flip flop Operation

For the two signals S&R there will be four states of operation like SR=00, 01,10,11. Let us see the output state for the first input pair. Before proceeding further first we will assume that already the output is in some state like Q=0 ,~Q=1. This is because as the two transistors are connected together to function as a flip flop, then the immediately after giving a power supply to the circuit the transistor output will be high or low due to cutoff ad saturation mode of transistors. This concept will be explained in the Bi-stable Multivibrator session.

1) The input condition SR=00, the Q=0 is fed back to the second NOR gate as shown in circuit diagram. The second NOR gate where the two inputs 0-0 results in output of 1 (i.e. ~Q=1). This ~Q is fed back to the first NOR gate and the resultant output  goes low i.e 0 (Q=0). Let us take in a reverse case i.e initial condition as Q=1 and ~Q=0. For the input signals SR(0-0), The second NOR gate output goes to active low ‘0’ condition for the two inputs Q-S(1-0) and further the first gate triggers to active high ‘1’ (Q=1). The above two cases has showed that for an input signals SR=00 the output state of SR flip flop remains the same i.e called “NO Change Sate”.

2)The second condition SR=01 with initial condition Q=1 and ~Q=0, the first gate which has two inputs ~Q-R = 0-1 triggers the output active high ‘0’ i.e Q = 1–>0. This Q is fed to the second gate with two inputs SQ=0-0 triggers the gate output to active high ‘1’ i.e ~Q= 0–>1. i.e. the assumed output high state triggered to low state by applying the R(RESET)=1. For the initial condition Q=0 and ~Q=1 and for the inputs SR=01 , the output of the flip flop will not change as it is already in active low state.

3) Third condition SR=10 with an initial condition Q=0 and ~Q=1, the second gate with two inputs SQ= 1-0 triggers the output to 0 i.e ~Q=1–>0. This ~Q signal is fed to the second gate with R as 0 which triggers the output to 1 i.e Q=0–>1. The initial low state of flip flop is changed to active high state i.e the output is SET for the input S=1. For the reverse initial condition Q=1 and ~Q=0 the output of flip flop does not change as it is already in SET state.

4) Last input condition is SR=11, assume the initial condition Q=0 and ~Q=1. The second gate output triggers to 0 for the two inputs SQ=1-0 i.e ~Q=1–>.0. This 0 output is fed to the first gate with R=1 and the output of the gate will be 0  i.e Q=0. Here in this case Q and ~Q has the same values which leads to ambiguity. This is not stable condition and an impractical state also called as forbidden state. this is major disadvantage of SR flip flop.

By summarizing above operations for various input conditions the below truth table shows the operating characteristics of S-R flip flop.

SR Flip flop Truth Table with NOR gates.

[table id=3 /]

RS Flip flop with NAND gates

This is complement to the NOR Gate flip as the if S and R equals to 0 then it leads to impracticable state and S and R equals to 1 leads to NO Change state.

Circuit diagram of RS flip flop with NAND Gates:

SR  FF With NAND Gate

SR FF With NAND Gate

Summarized Operation of RS Flip flop with NAND Gates

  1. SR = 0-0, For bidden state which is not a stable state.
  2. SR = 0-1, Sets the Flip flop i.e Q and ~Q goes to 1 and 0 i.e. SET state.
  3. SR = 1-0, Resets the Flip flop i.e. Q and ~Q goes to 0 and 1 i.e. RESET state.
  4. SR = 1-1, This no change state where the Q and ~Q remains in the same initial condition.

Truth Table For RS Flip-Flop With NAND gates

[table id=4 /]

 Applications of SR Flip

  • SR Flip flop is used in the Digital Logic circuit for the switch or the circuit breaker to hold the closed state even the input controlling signal disappears.
  • As a Digital latching relay it can be used.
  • As a switching mechanism for alarm circuit, that is when an alarm is pressed it will not get reset until the reset button is pressed.

 

 

 





     

  

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