What is self bias (or) voltage divide bias circuit of transistor?

The name self bias is coined because of the fact all the DC variations around Q-point tends to adjust itself in self bias circuit. The self bias circuit is shown below

Transistor self bias circuit

Transistor self bias circuit

All the capacitors shown in the figure acts as open circuit for DC and short circuit for AC signals. The self bias action can be explained as follows If Ic tends to increases due to increase in Ico (due to increase in temperature) the current through Re also increases. As a result voltage drop across Re also increases, hence base to emitter voltage decreases and base current decreases. Hence Ic increases less due to the action of self biasing resistor Re.

        Stability factor S = 1 + (Rb/Re) Where Rb = (R1*R2)/(R1+R2)

What is fixed bias?

The fixed bias circuit is shown in figure below:

Transistor fixed bias circuit

Transistor fixed bias circuit

Current Ib is constant in fixed bias circuit. The Fixed bias circuit offer poor stability variation in transistor parameters. In fixed bias circuit

                 Stability factor S = 1+β

Define stability factors of a transistor operated at Q-Point?

The main aim of biasing circuits is to stabilise the transistor’s operating point irrespective of variations in Ico, β, Vbe which vary because of varying temperature. Mainly the variation of Ico with temperature is a significant one and has to be taken care of. Accordingly a stability factor is defined o quantify the stability of biasing circuits with respect to variation in transistor parameters.

                                     Stability Factor S = Ic/ Ico

Similarly S’ = Ic/ β, S’’= Ic/ Vbe

What is thermal resistance of a transistor?

Thermal resistance is defined as the ration of steady state temperature raise at the collector junction to the power dissipated at the junction. It is expressed in Deg C/W and is given as

                                       Φ = (Tj-TA)/ PD


What is base width modulation or earlier effect?

Consider a transistor in common base configuration biased in active region of operation. As you increase collector to base voltage that is if you more reverse bias base collector junction the depletion layer width increases as depletion layer width is proportional to reverse bias voltage. This depletion layer protrudes more in to the base than collector because base is lightly doped compared to collector. As we increase base to collector voltage depletion layer width increases this in turn decreases effective base width. According to law of junction injected carrier concentration in base should reduce to zero at the onset of depletion layer in base. In the graph(plotted with minority carrier concentration on Y-axis and distance from emitter base junction to base collector junction on x-axis stands) shown below the left side is plotted for higher reverse bias compared to graph on right side with less slope compared to the one on the right .This is termed as Early effect.

base width modulation

base width modulation

Effects of the base width modulation?

Base width modulation (or) Early Effect has three main consequences

1. As emitter current is mainly diffusion current (assuming low level injection) now as collector base reverse bias increases hole concentration gradient increases, this leads to more emitter current (IE α ∆P/∆X).

2. Also as effective base width decreases there is less chance for recombination and base current decreases as reverse bias increases a base is mainly due to recombination currents, so beta current gain of common emitter transistor increases.

3. As we increase further the reverse bias voltage at some point effective base width approaches zero and transistor will breakdown .This phenomenon is called reach through or punch through.

What is high frequency model of transistor?

At high frequencies the low frequency small signal model of transistor has to be modified to include the effect of parasitic capacitances of transistor. Following is the high frequency model of a transistor.

high frequency model of transistor

high frequency model of transistor


B’ = internal node in base

Rbb’ = Base spreading resistance

Rb’e = Internal base node to emitter resistance

Ce = Diffusion capacitance of emitter base junction

Rb’e = Feedback resistance from internal base node to collector node

Gm = Transconductance

CC= transient capacitance of base collector junction

Express high frequency model parameters of a transistor in terms of small signal low frequency hybrid parameters?

Transconductance gm = Ic/Vt

 Internal Base node to emitter resistance rb’e = hfe/ gm = (hfe* Vt )/ Ic

Internal Base node to collector resistance rb’e = (hre* rb’c) / (1- hre) assuming hre << 1 it reduces to rb’e = (hre* rb’c)

Base spreading resistance rbb’ = hie rb’e = hie (hfe* Vt )/ Ic

Collector to emitter resistance rce = 1 / ( hoe – (1+ hfe)/rb’c)

What is the relation between large signal current gain (or) DC current gain and small signal beta?

The DC current gain is defined as the ratio of collector current to base current whereas small signal gain is the ratio of incremental change in collector current to the incremental change in base current.

              DC current gain βdc = Ic/Ib, small signal current gain β = hfe = Ic/ Ib at constant Vce

Since Ic = β*Ib + (1+β)*Icbo differentiating and rearranging the terms we get

                                   β = βdc/(1-(( Icbo+ Ib)*  βdc / Ic))

Where Icbo is reverse saturation current with surface currents e.t.c taken into account.

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